Examples of organic semiconductor materials exhibiting a mobility equivalent to that of amorphous silicon have been reported recently. An organic transistor using an organic semiconductor for the active layer does not require a manufacturing process at an extremely high temperature, and thus it is possible to manufacture a device easily with manufacturing equipment that is supplied at a low cost and that imposes a low environmental loading. Due to such advantages, the organic transistor is expected to be used as a semiconductor device to support the new electronic industry.
For improving the response speed of the organic transistor, it is indispensable to shorten the channel length as the distance between the source electrode and the drain electrode. However, when the channel length is shortened, the contact resistance between the organic semiconductor layer and the source and drain electrodes is increased in the proportions with respect to the channel resistance, and thus there has been a limit in improving the operation speed of the transistor even by shortening the channel length. For this reason, the response performance of an atmospherically-stable organic transistor reported up to now is still as low as the range from about 10 kHz to about 1 MHz.
The influences of the contact resistance between the organic semiconductor layer and the source and drain electrodes in a case where the channel length is shortened will be described in more detail below with reference to FIG. 10. FIG. 10 is a cross-sectional view showing an example of a typical structure of an organic transistor. In this organic transistor, a gate electrode 32 is provided on an insulating substrate 31, and a gate insulating layer 33 is formed thereon for coating the upper part. On the gate insulating later 33, a source electrode 34 and a drain electrode 35 are provided to be located at the both sides of the gate electrode 32. On the upper part of each of the source electrode 34 and the drain electrode 35, an organic semiconductor layer 36 is provided.
A cutoff frequency fc is the maximum frequency to which this organic transistor can respond, and it is defined in general as a frequency where the relationship between the gate current IG and the drain current ID becomes |IG|=|ID|.
Here, the on-state of the organic transistor is reviewed by using a so-called capacitor model of an aspect where the gate insulating layer 33 is sandwiched at both sides by the gate electrode 32 and the organic semiconductor layer 36 with a carrier injected. The impedance Z of the capacitor having a capacitance C is expressed as Z=1/(j·ω·C) (where j is an imaginary unit, and ω is an angular frequency). When the gate capacitance is CG and the gate voltage to be applied to the gate electrode 32 is VG;|IG/VG|=ωCG;namely, it can be expressed as follows.|IG|=ωCG|VG|  (1)
Next, |ID| will be mentioned. In the configuration of FIG. 10, the channel length is L, the channel width is W, and the electrical resistance between the source electrode 34 and the drain electrode 35 is represented by R (=RPS+RCH+RPD). RPS is a contact resistance generated during an electric charge transfer from the source electrode 34 to the organic semiconductor layer 36; RCH is a channel resistance in the channel when the organic semiconductor layer 36 is in an on-state, and RPD is a contact resistance during an electric charge transfer from the organic semiconductor layer 36 to the drain electrode 35.
Here, an electric conductivity σ in a solid is expressed as o=net where n is an electron density, e is an electron elementary quantity, and μ is a charge mobility. Taking the above-described capacitor model into consideration, an electric charge ne present around the unit area of the channel is expressed as follows, where ci is a gate capacitance per channel unit area of the organic transistor in an on-state.ne=ciVG 
When the contact resistance between the organic semiconductor material 36 and the source and drain electrodes 34, 35 is insignificant, it will be as follows.R=RCH=(1/σ)×(L/W)
The drain current ID that flows from the source electrode 34 to the drain electrode 35 can be expressed by Equation (2) below by using σ=neμ where VD represents the drain voltage.ID=VD/RCH=σ(W/L)VD=(ciVGμ)(W/L)VD  (2)Therefore, from Equation (1) and Equation (2), by substituting ω=2πfC assuming that |IG|=|ID|, the equation below is obtained.fC={μVD/(2πL2)}×(ciWL/CG)  (3)ciWL corresponds to the capacitance at the channel part. The term of (ciWL/CG) indicates the ratio of the capacitance at the channel part to the total gate capacitance including parasitic capacitance, which expresses that the response speed is in proportions to this ratio.
It is evident from Equation (3) that in a case where the contact resistance with the electrode is insignificant, the maximum operation frequency can be increased rapidly in proportions to the reciprocal of L2 by shortening the channel length L.
In a case where the contact resistance with the electrode is significant, the apparent mobility μeff for which the contact resistance is taken into consideration (hereinafter recited as effective mobility) is defined as satisfying Equation (4) below.ID=VD/R=(ciVGμeff)(W/L)VD  (4)When expressing the sum of the contact resistance as RP=RPS+RPD, and using a recitation R=RCH+RP, the relationship between the effective mobility μeff and the charge mobility μ inherent in the material is arranged as in the equation below by use of Equation (2) and Equation (4).μeff=μ/{1+RP×(c1VGμ)×(W/L)}  (5)In this equation, when the contact resistance RP=0, it can be confirmed that μeff=μ.
Further, Equation (5) shows that in a case where the contact resistance exists, the degree that the effective mobility μeff is lowered from the inherent μ is increased along with the channel length L is shortened.
In this case, the cutoff frequency fC is as follows.fC={μeffVD/(2πL2)}×(ciWL/CG)  (6)
This indicates that in a case where the effective mobility μeff is lowered accompanying the shortening of channel, it is difficult to raise the operation frequency. Therefore, it is considerably important to construct a short channel device with the influence of the contact resistance reduced as much as possible for the purpose of enhancing the operation speed of the organic transistor.
The device structures of typical organic transistors are classified into two types, i.e., a top contact type and a bottom contact type. The top contact type refers to a structure where a source electrode and a drain electrode are formed on a semiconductor layer at the side opposite to a gate electrode. The bottom contact type refers to a structure as shown in FIG. 10, where a source electrode and a drain electrode are formed at the lower part of a semiconductor layer.
In a case of a top contact type, the path for the drain current is as follows. Namely, the current flows from the source electrode at the upper part through the semiconductor layer in the thickness direction, later it flows through the channel part and then flows again through the semiconductor layer in the thickness direction to reach the drain electrode. Generally in such a case, since the mobility in the thickness direction of the organic semiconductor layer is often lower than the mobility in the channel direction, a technique to form an extremely thin organic semiconductor layer is required. Furthermore, when fabricating a top contact type structure with a short channel length by use of a micromachining process such as photolithography, a photolithography process has to be carried out after fabricating the organic semiconductor layer. However in general, since the organic semiconductor layer frequently is damaged during the photolithography process, the process cannot be employed. As a result, the channel length cannot be shortened sufficiently, thereby making difficult to achieve a high-speed response performance.
In a case of a device structure of a bottom contact type, the thickness direction of the organic semiconductor layer is not included as the path for the drain current, and thus only the source and drain electrodes and the channel plane are taken into consideration. Another advantage is that since an organic semiconductor layer is fabricated after constituting a fine short channel by forming the source and drain electrodes by photolithography, the channel length can be shortened. However in general, there is a problem that in a device fabricated as a bottom contact type, the contact resistance between the electrode and the organic semiconductor is greater in comparison with the case of the top contact type. For this reason, in order to increase the response speed of the transistor, attempts for lowering the contact resistance between an electrode and an organic semiconductor have been made while employing the bottom contact type.
Examples thereof include a method of suppressing a parasitic resistance by forming a self-assembled monolayer (SAM) having a film thickness of several nanometers on a gold electrode that serves as source and drain electrodes; and a technique of coordinating the energy level of the organic semiconductor and the work function of the electrode.
Further, Patent Document 1 discloses employing a gold-based alloy, namely an alloy containing gold in the range not less than 67 atomic % and not more than 97 atomic % for an adhesion layer to be provided between the source and drain electrodes made of gold and the insulating substrate. For the material to form the source and drain electrodes of an organic transistor of p-type operation, gold whose work function is approximate to the HOMO level of the organic transistor is used often. However, as gold has lower adhesion to other materials, a technique of forming an adhesion layer between the gold electrode and the substrate is carried out in general, and it has been pointed out that this adhesion layer causes the parasitic resistance between the source and drain electrodes and the organic semiconductor layer. To cope with this problem, as mentioned above, Patent Document 1 discloses a technique for reducing the parasitic resistance between the organic semiconductor layer and the electrodes by using an alloy including gold as the material of the adhesion layer. However, even in the organic transistor disclosed by Patent Document 1, the effective mobility is still as low as the range of about 0.4 to about 2.2 cm2/Vs.
This is considered to be caused by the presence of a level difference between the upper surfaces of the source and drain electrodes and the upper surface of the gate insulating layer between these electrodes. Namely, the organic semiconductor layer formed in the region of this level difference is deformed in comparison with a layer formed on a flat surface, and thus a disturbance in the molecular orientation occurs, thereby hindering the improvement in mobility. Further, such a deformation in the organic semiconductor layer will cause also an increase in the contact resistance between the organic semiconductor layer and the source and drain electrodes. For this reason, when the channel length is short, the disturbance in the molecular orientation is inevitable, and thus it is difficult to obtain a high effective mobility with a short channel.
For avoiding the deformation of the organic semiconductor layer caused by the level difference and for providing an organic semiconductor layer in a flat state, the employment of the gap structure disclosed by Non-Patent Document 1 can be taken into consideration. The gap structure is one aspect of a bottom contact type device structure. A stepped structure is provided on the insulating substrate, and on this stepped structure a source electrode and a drain electrode are provided respectively and independently. A single crystal organic semiconductor is supported on the source and drain electrodes on the upper surfaces of the level difference, forming the device structure in which the single crystal organic semiconductor bridging the source electrode and the drain electrode is flat.
Between the substrate and the lower surface of the single crystal organic transistor in the area between the source electrode and the drain electrode, a space, i.e., a gap is formed. The gate electrode formed on the substrate between the source and drain electrodes opposes the single crystal organic semiconductor across the gap. The source and drain electrodes are formed respectively on a pair of pedestals formed spaced apart from each other on the substrate, and the gate electrode is formed on the substrate between the pair of pedestals. According to this device structure, the single crystal organic semiconductor opposes the gate electrode across an air layer. Therefore, in comparison with a conventional and typical structure where an insulating solid that composes the gate insulating layer and the organic semiconductor are in contact with each other, it is possible to prevent lowering of the mobility caused by impurities or the like in the interface between the gate insulator and the organic semiconductor. Thus it is possible to calculate with further preciseness the charge mobility inherent in the single crystal organic semiconductor material.
It should be noted, however, that in Non-Patent Document 1, the gap device structure is employed to evaluate the electronic conduction on the organic single crystal interface, but a structure for shortening the channel length so as to allow a high-speed response is not disclosed.